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IDT54/74FCT543T/AT/CT/DT FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS OCTAL LATCHED TRANSCEIVER
FEATURES:
* * * *
IDT54/74FCT543T/AT/CT/DT
* * * * *
Std., A, C, and D grades Low input and output leakage 1A (max.) CMOS power levels True TTL input and output compatibility: - VOH = 3.3V (typ.) - VOL = 0.3V (typ.) High Drive outputs (-15mA IOH, 64mA IOL) Meets or exceeds JEDEC standard 18 specifications Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Power off disable outputs permit "live insertion" Available in the following packages: - Industrial: SOIC, SSOP, QSOP - Military: CERDIP, LCC
DESCRIPTION:
The FCT543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be low in order to enter data from A0-A7 or to take data from B0-B7, as indicated in the Function Table. With CEAB low, a low signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent; a subsequent low-tohigh transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both low, the 3-state B output buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses the CEBA, LEBA and OEBA inputs.
FUNCTIONAL BLOCK DIAGRAM
DETAIL A D LE A0 Q D LE Q B0
A1 A2 A3 A4 A5 A6 A7 DETAIL A x 7
B1 B2 B3 B4 B5 B6 B7
OEBA OEAB CEBA LEBA CEAB LEAB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
JUNE 2002
DSC-5489/2
(c) 2002 Integrated Device Technology, Inc.
IDT54/74FCT543T/AT/CT/DT FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEBA CEBA
27
NC
A0
OEBA A0 A1 A2 A3 A4 A5 A6 A7 CEAB GND
2 3 4 5 6 7 8 9 10 11 12
23 22 21 20 19 18 17 16 15 14 13
CEBA B0 B1 B2 B3 B4 B5 B6 B7 LEAB OEAB A1 A2 A3 NC A4 A5 A6
5 6 7 8 9
4
3
2
28 1
26 25 24 23 22 21 20 19 18
B0
INDEX
Vcc
LEBA
1
24
VCC
LEBA
B1 B2 B3 NC B4 B5 B6
10 11 12 13 14 15 16 17
CEAB
OEAB
LEAB
GND
NC
A7
CERDIP/ SOIC/ SSOP/ QSOP TOP VIEW
LCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max -0.5 to +7 -0.5 to VCC+0.5 -65 to +150 -60 to +120 Unit V V C mA VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TSTG IOUT Storage Temperature DC Output Current
PIN DESCRIPTION
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0-A7 B0-B7
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only.
Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
2
B7
IDT54/74FCT543T/AT/CT/DT FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1, 2)
Inputs LEAB X H X L H
For A-to-B (Symmetric with B-to-A)
CEAB H X X L L OEAB X X H L L Latch Status A-to-B Storing Storing X Transparent Storing Output Buffers B0-B7 High Z X High Z Current A Inputs Previous* A Inputs
NOTES: 1. * Before LEAB LOW-to-HIGH Transition H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA and OEBA.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 5%; Military: TA = -55C to +125C, VCC = 5.0V 10%
Symbol VIH VIL IIH IIL IOZH IOZL II VIK VH ICC Parameter Input HIGH Level Input LOW Level Input HIGH Current(4) Input LOW Current(4) High Impedance Output Current (3-State output pins)(4) Input HIGH Current(4) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) VCC = Min, IIN = -18mA -- VCC = Max., VIN = GND or VCC Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VCC = Max. VCC = Max VI = 2.7V VI = 0.5V VO = 2.7V VO = 0.5V Min. 2 -- -- -- -- -- -- -- -- -- Typ.(2) -- -- -- -- -- -- -- -0.7 200 0.01 Max. -- 0.8 1 1 1 1 1 -1.2 -- 1 A V mV mA Unit V V A A A
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = Min IOH = -6mA MIL VIN = VIH or VIL IOH = -8mA IND IOH = -12mA MIL IOH = -15mA IND VCC = Min IOL = 48mA MIL VIN = VIH or VIL IOL = 64mA IND VCC = Max., VO = GND(3) VCC = 0V, VIN or VO 4.5V Min. 2.4 2 -- -60 -- Typ.(2) 3.3 3 0.3 -120 -- Max. -- -- 0.55 -225 1 V mA A Unit V
VOL IOS IOFF
Output LOW Voltage Short Circuit Current Input/Output Power Off Leakage(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is 5A at TA = -55C. 5. This parameter is guaranteed but not tested.
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IDT54/74FCT543T/AT/CT/DT FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) VCC = Max. VIN = 3.4V(3) VCC = Max., Outputs Open CEAB and OEAB = GND CEBA = VCC One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fCP = 10MHz (LEAB ) 50% Duty Cycle CEAB and OEAB = GND CEBA = VCC One Bit Toggling at fi = 5MHz 50% duty cycle VCC = Max., Outputs Open fCP = 10MHz (LEAB ) 50% Duty Cycle CEAB and OEAB = GND CEBA = VCC Eight Bits Toggling at fi = 2.5MHz 50% duty cycle VIN = VCC VIN = GND Test Conditions(1) Min. -- -- Typ.(2) 0.5 0.15 Max. 2 0.25 Unit mA mA/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND VIN = 3.4V VIN = GND VIN = VCC VIN = GND VIN = 3.4V VIN = GND
--
1.5
3.5
mA
--
2
5.5
--
3.8
7.3(5)
mA
--
6
16.3(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT54/74FCT543T/AT/CT/DT FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
74FCT543AT Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Parameter Propagation Delay Transparant Mode Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Output Enable Time OEBA or OEAB to Ax or Bx CEBA or CEAB to Ax or Bx Output Disable Time OEBA or OEAB to Ax or Bx CEBA or CEAB to Ax or Bx Set-up Time, HIGH or LOW Ax or Bx to LEBA or LEAB Hold Time, HIGH or LOW Ax or Bx to LEBA or LEAB LEBA or LEAB Pulse Width LOW 5 -- 5 -- 3(3) -- ns 2 -- 2 -- 1.5 -- ns 2 -- 2 -- 1.5 -- ns 1.5 7.5 1.5 6.5 1.5 4.3 ns 1.5 9 1.5 8 1.5 5.4 ns 1.5 8 1.5 7 1.5 5 ns Condition(1) CL = 50pF RL = 500 Min.(2) 1.5 Max. 6.5 74FCT543CT Min.(2) 1.5 Max. 5.3 74FCT543DT Min.(2) 1.5 Max. 4.4 Unit ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
54FCT543T Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW Parameter Propagation Delay Transparant Mode Ax to Bx or Bx to Ax Propagation Delay LEBA to Ax, LEAB to Bx Output Enable Time OEBA or OEAB to Ax or Bx CEBA or CEAB to Ax or Bx Output Disable Time OEBA or OEAB to Ax or Bx CEBA or CEAB to Ax or Bx Set-up Time, HIGH or LOW Ax or Bx to LEBA or LEAB Hold Time, HIGH or LOW Ax or Bx to LEBA or LEAB LEBA or LEAB Pulse Width LOW 5 -- 5 -- 5 -- ns 2 -- 2 -- 2 -- ns 3 -- 2 -- 2 -- ns 1.5 13 1.5 8.5 1.5 7.5 ns 1.5 14 1.5 10 1.5 9 ns 1.5 14 1.5 9 1.5 8 ns Condition(1) CL = 50pF RL = 500 Min.(2) 1.5 Max. 10 54FCT543AT Min.(2) 1.5 Max. 7.5 54FCT543CT Min.(2) 1.5 Max. 6.1 Unit ns
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This limit is guaranteed but not tested.
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IDT54/74FCT543T/AT/CT/DT FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T . VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open
50pF CL
500
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
Octal link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
Octal link
DISABLE 3V 1.5V
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPHZ 0.3V 1.5V 0V tPLZ
0V 3.5V 0.3V VOL VOH 0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns.
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IDT54/74FCT543T/AT/CT/DT FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXX IDT XX FCT Device Type Temp. Range XX Package X Process Blank B Industrial MIL-STD-883, Class B Industrial Options Small Outline IC Shrink Small Outline Package Quarter-size Small Outline Package Military Options CERDIP Leadless Chip Carrier
SO PY Q D L
543T 543AT 543CT 543DT 54 74
Fast CMOS Octal Latched Transceiver
- 55C to +125C - 40C to +85C
DATA SHEET DOCUMENT HISTORY 6/24/2002 Updated as per PDNs Logic-00-07 and Logic-01-04
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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